1. Field of the Invention
The present invention generally relates to subscriber circuits and, more particularly, to a subscriber circuit which can be used both as a subscriber circuit for an analog system and a subscriber circuit for a digital system.
2. Description of the Related Art
In a digital telephone system, a basic-rate subscriber circuit transmitting a digital signal (according to the 2B1Q system or the ping-pong system) is used. In an analog telephone system, a subscriber circuit for transmitting a sound signal is used. Hereinafter, a subscriber circuit for a digital subscriber system will be referred to as a digital subscriber circuit, and a subscriber circuit for an analog subscriber system will be referred to as an analog subscriber circuit,
In the past, an analog subscriber circuit and a digital subscriber circuit are implemented by different circuits since, the digital system carries two times as much information as the analog system and is also different from the analog system in a signal symbol and a signal voltage used in the system.
FIG. 1 is a table comparing the analog subscriber circuit, the digital subscriber circuit for the 2B1Q system and the digital subscriber circuit for the ping-pong system, with respect to a signal symbol, a signal speed, a signal amplitude and termination.
For example, the signal speed of the analog system is 300-3400 Hz, the signal speed of the 2B1Q system is 160kbps and the signal speed of the ping-pong system is 320 kbps. The signal amplitude of the analog system is 1.55V.sub.OP (V.sub.OP indicates a voltage between 0 and a peak value). The signal amplitude of the 2B1Q system is 2.5V.sub.OP and the signal amplitude of the ping-pong system is 6V.sub.OP. The termination resistance of the analog system is 600 .OMEGA., the termination resistance of the 2B1Q system is 135 .OMEGA. and the termination resistance of the ping-pong system is 110 .OMEGA..
Accordingly, when a subscriber wants a change from an analog system to a digital system (2B1Q or ping-pong), it is necessary to manually substitute a new printed circuit board (PCB) for an existing one.
For example, if a system is installed in a location away from an exchange, a maintenance person must be called in to exchange PCBs. Thus, it is time-consuming and uneconomical to shift from one type of system to another.
Accordingly, it is demanded that both the analog facilities and the digital facilities are implemented by the same PCB.
FIG. 2 shows a construction of an analog subscriber circuit according to the related art.
Referring to FIG. 2, a codec 1 performs conversion of a sound signal. The codec 1 is connected between a subscriber circuit and a highway (HW). A data input terminal (D-IN) and a data output terminal (D-OUT) are connected to the highway.
A digital sound signal is converted into an analog signal by the codec 1 and output from an analog output terminal (A-OUT). A received signal is fed to an analog input terminal (A-IN). A feedback circuit 2 is connected between the analog input terminal A-IN and the analog output terminal A-OUT. The feedback circuit 2 is formed by an internal termination resistance 2a.
Amplifiers 3 and 4 receive an analog output of the codec 1 so as to amplify the same (the amplifier 4 is an inversion amplifier). A bias voltage supply unit 5 receives outputs of the amplifiers 3 and 4 so as to provide a bias voltage. The bias voltage supply unit 5 is formed by a bias circuit 5a. A power supply voltage V.sub.BB (-48V) is supplied to the bias circuit 5a.
A signal output unit 6 receives an output of the bias voltage supply unit 5 and outputs a sound signal. The signal output unit 6 consists of amplifiers AP1 and AP2 constituting a buffer amplifier. Operation amplifiers are used to construct these amplifiers AP1 and AP2. A phase compensation circuit 7 performs phase compensation for these amplifiers and is implemented by a capacitor C1.
An output of the amplifier AP1 is connected to line A via an external termination resistance R, and an output of the amplifier AP2 is connected to line B via an external termination resistance R. A telephone set (not shown) is connected between line A and line B. A signal reception unit 8 receives the sound signal from line A and line B and is formed by a differential amplifier AP3. The differential amplifier AP3 is implemented by an operational amplifier, and the output of the signal reception unit AP3 is connected to the analog input terminal A-IN of the codec 1 described above.
A description will be given of an operation of the circuit constructed above.
The analog subscriber circuit of FIG. 2 superimposes an analog signal of 300 Hz-3400 Hz and a maximum level of 3.17 dBmO (zero-relative level) to an bias voltage generally having a level of -48 V, as a differential signal, and outputs the superimposed signal to the subscriber lines (line A, line B). The zero-relative level indicates a level with respect to a reference level of 0.
For example, in the case of an impedance line of 600 .OMEGA., a voltage level for supplying lmW to the impedance line of OdBmO=600 .OMEGA. is 0.775 (V).
A signal for transmission is output from the analog output terminal (A-OUT) of the codec 1, amplified by the amplifiers 3 and 4, and superimposed on the bias voltage by the bias voltage supply unit 5. Each output of the bias circuit 5a is fed to line A and line B of the subscriber as a differential analog signal from the signal output amplifiers AP1 and AP2.
The received signal is input to the differential amplifier AP3 of the signal reception unit 8, connected to the internal termination resistance 2a, and input to the analog input terminal (A-IN) of the codec 1. The received signal is fed back via the feedback circuit 2 to the signal output unit, so that termination of the two lines is effected.
In this way, in an analog subscriber circuit, a feedback system involving many amplifiers is produced so that the termination is effected accordingly. The phase compensation circuit 7 is provided for each of the operational amplifiers AP1 and AP2 so as to prevent oscillation and provide proper phase compensation.
FIG. 3 shows a construction of an operational amplifier. Because feedback is employed in the analog subscriber circuit, the phase compensation circuit 7 is provided so as to prevent oscillation. FIG. 4 is a graph showing a gain-frequency characteristic of the operational amplifier used in a subscriber circuit. The gain (dB) is vertically plotted and the frequency (Hz) is horizontally plotted. The graph of FIG. 4 is called a Bode diagram.
Curve f1 indicates an open loop characteristic of the amplifier, wherein phase compensation is not performed. The characteristic as indicated by curve f1 is used in the ping-pong system. Referring to curve f1, stages are produced at 6 dB/oct and 12 dB/oct. Inclination at 12 dB/oct; indicates that the output phase is 180.degree. displaced with respect to the input so that a negative feedback ends; up as a positive feedback. If the feedback circuit remains unmodified, oscillation results.
Curve f2 indicates a frequency characteristic, wherein phase compensation is performed. The characteristic as indicated by curve f2 is used in the 2B1Q system. Curve f3 indicates a frequency characteristic, wherein sufficient phase compensation is performed so that oscillation is not caused in the circuit even when feedback is performed. The characteristic as indicated by curve f3 is used in the analog system. Inclination of curve f3 is 6 dB/oct.
Referring to FIG. 2, the external termination resistance R coupled to the subscriber line is provided as a protection resistance of, for example, 50 .OMEGA.. For example, when the termination of 600 .OMEGA. is to be implemented, the feedback circuit provides the remaining 500 .OMEGA. (=600-50.times.2).
FIG. 5 shows a construction of a conventional subscriber circuit for the 2B1Q system. In FIGS. 2 and 5, like numerals designate like elements. The 2B1Q system uses digital signals of four levels (+3, -3, +1, -1). A frequency spectrum of 40 kHz-80 kHz is required.
Referring to FIG. 5, the subscriber circuit comprises an interface unit provided between the subscriber circuit and the highway (HW), amplifiers 3 and 4 for amplifying an output signal, and a signal output unit 6 for receiving an output of the amplifiers 3 and 4. The signal output unit 6 consists of operational amplifiers AP1 and AP2. Capacitors C2 are coupled to the operational amplifiers AP1 and AP2 so as to constitute phase compensation circuits 7. The value of the capacitor C2 is controlled to be smaller than the value of the capacitor C1 in the analog subscriber circuit shown in FIG. 2.
A transformer T1 has its secondary side connected between the operational amplifiers AP1 and AP2. The primary winding of the transformer T1 is connected to line A and line B. A power feed circuit 10 supplies a dc current to the transformer T1. A capacitor C is coupled to the secondary side of the transformer T1. The location of the capacitor C indicates a midpoint of the primary side of the transformer T1. An output of the signal reception unit 8 is fed to an interface unit 9. The signal reception unit 8 is formed by a differential amplifier AP3. A description will be given of the circuit constructed above.
The signal for transmission is turned into a differential signal by the signal output unit 6 and output to line A and line B (subscriber lines) via the transformer T1. A dc component supplied by the power feed circuit 10 via the midpoint (location of the capacitor C) is superimposed on the signal for transmission.
The received signal is input to the operational amplifier AP3 of the signal reception unit 8 via the subscriber line and the transformer T1. The termination is determined by the wound resistance and the turn ratio of the transformer T1, and also by the value of the resistance R. Accordingly, the internal termination such as that in the analog subscriber circuit is not performed. In order to prevent oscillation of the signal output unit 6, the phase compensation circuit 7 having the characteristic indicated by curve f2 of FIG. 4 is coupled to the operational amplifiers AP1 and AP2 of the signal output unit 6.
FIG. 6 shows a construction of the subscriber circuit of the ping-pong system. In FIGS. 5 and 6, like numerals designate like elements. The ping-pong system is constructed such that transmission and reception are alternately repeated. The time-division multiplexed signal of 6V.sub.OP and 160 kbs is transmitted and received, resulting in substantially transmitting and receiving a high-speed 320 kbs AMI signal.
Referring to FIG. 6, an interface/control unit 11 provides an interface and control of the signal. The amplifiers 3 and 4 amplifies the signal for transmission. The operational amplifiers AP1 and AP2 receive outputs from the amplifiers 3 and 4. The operational amplifiers AP1 and AP2 constitute the signal output unit 6. Unlike, the analog system and the 2B1Q system, phase compensation of the operational amplifiers is not provided.
A transformer T2 has a secondary side thereof connected between the operational amplifiers AP1 and AP2. The primary side of the transformer T2 is supplied with the dc component by the power feed circuit 10, with the ac component cut by the capacitor C.
A signal reception switching unit 12 connects the secondary side of the transformer T2 to the signal reception unit 8 when the signal is received. A control from the interface/control unit 11 controls the switch of the signal reception switching unit 12 so as cause it to be turned off when the signal is transmitted and turned on when the signal is received. A description will now be given of the operation of the circuit constructed as described above.
The circuit of FIG. 6 is constructed such that the signal reception switching unit 12 connects the received signal to the signal reception unit 8. When the signal is transmitted, the signal reception unit 8 is disconnected. Alternatively, in a transmission, the reception unit is configured not to receive the signal.
The signal for transmission is supplied via the output terminal OUT of the interface/control unit 11 to the signal output unit 6. The signal output unit 6 produces a differential signal accordingly and superimpose it on the dc component supplied by the power feed circuit 10 via the transformer T2. The superimposed signal is output to the subscriber lines (lines A and B).
The received signal arriving via the subscriber line is input to the differential amplifier AP3 of the signal reception unit 8 via the transformer T2 and the signal reception switching unit 12. The received signal is fed to the input terminal IN of the interface/control unit 11 via the amplifier AP3.
The termination is determined by the wound resistance and the turn ratio of the transformer T2, and the value of the resistance R. In this circuit, it is not necessary to provide a phase compensation circuit for the operational amplifiers AP1 and AP2 of the signal output unit 6. Phase compensation is not performed since the signal of an even higher speed is received than in the 2B1Q system.
The three systems described above are completely different in the circuitry. The difference derives mainly from the frequency of the output signal and how the termination is provided.
A first problem arises due to a difference in the phase compensation bandwidth used by the operational amplifier. In the analog system, sufficient phase compensation is necessary. In the 2B1Q system, the phase compensation must be controlled to a minimum level since the broadband is used than in the analog system. In the ping-pong system, a signal of an even higher speed is received so that the phase compensation circuit can not be provided. Accordingly, it has been difficult to implement the three systems in a single circuitry.
A second problem pertains to the speed of the operational amplifier. Phase compensation inherently restricts the broadband characteristic. In the 2B1Q system, a sufficient broadband characteristic need be ensured prior to phase compensation.
The operational amplifier operated on a high voltage of 48V is necessary. The transistors constituting the operational amplifier have a high withstand voltage and the size thereof is relatively large. Since a large transistor element has a parasite capacity (C.sub.OP) and is not adapted for the high-frequency (broadband) range.
The following problems exist in a high-frequency operation.
In the high-frequency operation, small devices are necessary. This shows that only the transistor with a low withstand voltage can be used.
Secondly, a large current is to be introduced. This means that the resultant circuitry requires a relatively large power consumption.
Accordingly, it is difficult to produce operational amplifiers with a high withstand voltage and a broadband characteristic.
A description will be given of a background regarding a difference between a power feed circuit for the analog system and that for the digital system.
FIG. 7 shows an equivalent circuit of a power feed circuit for the analog system, illustrating a principle of an analog power feed circuit. A power feed circuit 1001 supplies an current, a subscriber line 1003 is connected to an output of the power feed circuit 1001, a load 1002 has an current flowing therein. A telephone set is used as the load 1002.
A series circuit formed by a resistance and an inductance is provided at an current exit and an current inlet of the power feed circuit 1001. L1 indicates an inductance, R1 indicates a resistance, L2 indicates an inductance, and R2 indicates a resistance. For example, the inductances L1, are on the order of several H, the resistances R1, R2 are on the order of 200 .OMEGA.. T1 indicates a sound coupling transformer for a call.
When the telephone set 1002 is set in a off-hook state in such a system, a loop is formed, so that a load current (output current) IL flows in the telephone set 1002. FIG. 8 shows a characteristic of the analog power feed circuit, assuming a voltage between the subscriber lines 1003 is Vab. In FIG. 8, the line voltage Vab is horizontally plotted and the output current IL is vertically plotted. As shown in FIG. 8, the analog power feed circuit provides constant-resistance power feed.
FIG. 9 illustrates a principle of a digital power feed circuit. In FIGS. 7 and 9, like numeral indicate like components. A load current IL provided by a power supply transformer T2 is caused to flow in a terminal unit (DSU) 1004 via the subscriber line 1003 and a choke coil L1 after being rectified by a diode D1. The terminal unit 1004 is connected to a terminal adapter (TA) 1005 which is connected to a terminal 1006 embodied by, for example, a telephone set. T indicates a coupling transformer.
FIG. 10 shows a characteristic of an output current IL of the circuit constructed in this way. In FIG. 10, a line voltage Vab is horizontally plotted, and an output current IL is vertically plotted. As is obviously learned from FIG. 10, the digital power feed circuit provides a constant-current characteristic. For example, a constant current of approximately 39 mA flows.
The analog power feed circuit is different from the digital power feed circuit in the characteristic required thereof. The analog power feed circuit provides constant-resistance power feed, and must provide a high impedance so that a sound does not leak out to a power supply unit at a sound frequency (100-4 kHz).
In contrast, the digital power feed circuit provides constant-current power feed, as shown in FIG. 10, and processes a digital signal of higher frequency than a signal of the analog system. In order to prevent the signal from migrating to a power supply unit, the digital power feed circuit must provide a high impedance. The digital system also adopts a floating power feed system in order to keep a proper ground balance.
Another difference between the analog system and the digital system resides in a signal transmission and reception circuit. In the digital system, transmission and reception of a signal is performed by a transformer. This is because a digital signal contains high-frequency components so that there are not any suitable signal transmission device other than a transformer.
Due to a characteristic inherent in a transformer, it is difficult to produce a transformer which can operate in a high frequency zone covering a range between a sound frequency band of the analog system and a several-MHz zone of the digital system. FIG. 11 is a graph showing a gain characteristic of an analog transformer and a digital transformer. A logarithm of the frequency is horizontally plotted, and a gain of a transformer is vertically plotted. f1 indicates a characteristic of the analog transformer, and f2 indicates a characteristics of the digital transformer. As shown in FIG. 11, there is no frequency area where a high gain zone of the transformers overlap.
Thus, the analog power feed circuit and the digital power feed circuit are totally different from each other so that it has been difficult to adapt the same circuit for both the analog system and the digital system. Installing both circuits and switching between the circuits is uneconomical since one of the circuits remains unused while the other is being used. Installing two circuits is also disadvantageous in that it causes the circuit scale to grow excessively.
Another aspect of the present invention concerns a switching power supply.
FIG. 12 shows a construction of a switching power supply circuit according to the related art. Referring to FIG. 12, the switching power supply circuit comprises a load 2001 connected between terminal A and terminal B of a power supply. In this example, the load 2001 is embodied by a telephone set. That is, the power supply circuit of FIG. 12 functions as a power feed circuit for the telephone set.
The power supply circuit of FIG. 12 also comprises a switching circuit 2002 for performing switching using a switching element embodied by a transistor TR. A primary winding L1 of a high-frequency transformer is connected as a collector load of the transistor TR. That is, a dc voltage VBB is applied to a series circuit formed by the primary winding L1 and the transistor TR.
The power supply circuit further comprises a secondary winding L2 of the high-frequency transformer, a rectifying diode D2 connected in series with the secondary winding L2, a choke coil L3 connected in series with the diode D2, and a diode D1 connected in parallel with the series circuit formed by the secondary winding L2 and the diode D2. The diode D1 is provided to form a loop when the energy stored in the choke coil L3 causes a current to flow in the load, when the diode D2 is switched off.
A capacitor C1 is connected between an end of the choke coil L3 and a common line. The capacitor C1 and the choke coil L3 forms a smoothing circuit. A high-frequency alternate current generated in the secondary winding of the transformer T responsive to the switching by the transistor TR is rectified. After being rectified, the current is smoothed by the smoothing circuit.
A current detection resistance R3 detects a current in the load 2001. An output current detection resistance 2003 receives a voltage generated across the resistance R3 and generates a signal Vdc commensurate with an output current. An error amplifier 2004 compares an output voltage Vdc of the current detection circuit 2003 and a reference voltage Vst and generates a signal commensurate with a difference thereof. The error amplifier 2004 is composed of a resistance R1 for receiving the voltage Vdc, an operational amplifier U1, a feedback resistance R2 connected between an input and an output of the operational amplifier U1, and a Capacitor C2 connected in parallel with the feedback resistance R2. The output voltage Vdc is fed to one of the inputs of the operational amplifier U1. The other input of the operational amplifier U1 is supplied with a reference voltage Vst.
A duty control circuit 2005 compares the output of the error amplifier 2004 and a sawtooth wave and generates a PWM pulse signal. The duty control circuit 2005 controls the switching transistor TR so as to vary an on-time thereof. A buffer 2006 is a driver circuit which receives the output of the duty control circuit 2005. The output of the buffer 2006 drives the switching transistor TR.
A description will be given of the operation of the circuit constructed in this way.
In a normal operation, the duty control circuit 2005 outputs the PWM signal of a constant duty ratio so as to switch the switching transistor TR. The dc voltage VBB is turned on/off at a constant duty ratio. The high-frequency alternate current is generated in the secondary side of the high-frequency transformer T. The generated high-frequency alternate current is rectified by the rectifying diode D2.
While the switching transistor TR is on, a current flows in a circuit connected to the secondary side of the high-frequency transformer T. That is, a current flow in a loop connecting the secondary coil L2, the diode D2, the choke coil L3, the resistance R3, the load 2001, the secondary coil L2. In this state, the capacitor C1 is charged. The smoothing circuit formed by the choke coil L3 and the capacitor C1 converts a dc ripple current into a flat dc voltage. When the switching transistor TR is off, the energy stored in the choke coil L3 causes a current to flow in a loop connecting the diode D1, the choke coil L3, the resistance R3, the load 2001, the diode D1. In this way, the load current (output current) Idc continually flows in the load 2001.
When the load current drops due to some cause, the error amplifier 2004 supplies a control signal to the duty control circuit 2005 so as to increase an on-time of the transistor TR. Conversely, when the load current increases for some reason, the error amplifier 2004 supplies a control signal to the duty control circuit 2005 to decrease an on-time of the transistor TR. With such PWM control, the load current Idc is controlled so as to be maintained at a constant level. That is, when the output drops, the output level of the error amplifier 2004 drops so that the duty control circuit 2005 outputs the PWM pulse having a duty ratio which causes the on-time to increase. When the output increases, the output level of the error amplifier 2004 increases so that the duty control circuit 2005 outputs the PWM pulse having a duty ratio which causes the on-time to decrease. In this way, the output is maintained at a constant level.
FIG. 13 is a flowchart showing the operation of the circuit according to the related art. The output current detection circuit 2003 detects the current Idc and outputs the voltage Vdc proportional to the current Idc (S1). The error amplifier 2004 is provided by the reference voltage generating unit with the voltage Vst corresponding to a target current (S2). The error amplifier 2004 feeds the voltage obtained by amplifying a difference voltage (error) between the detected voltage Vdc and the reference voltage Vst, to the duty control circuit 2005 (S3). The error amplifier 2004 forms an integrator (low-pass filter) so as to cause the output to vary gradually in the presence of an abrupt change in the level of Vdc.
The duty control circuit 2005 continually generates a sawtooth wave or a triangular wave, compares the output of the error amplifier 2004 with the sawtooth wave or the triangular wave, so as to generate a PWM clock (PWM pulse) (S4). Given the constant sawtooth wave, the duty of the PWM pulse (ratio of on-time of the transistor in a given period of time) changes due to increase and decrease of the dc level of the error amplifier 2004. Finally, the negative feedback circuit shown in FIG. 13 phases out to a state Vdc=Vst.
The driver circuit (the buffer 2006) drives the switching transistor TR of the switching circuit 2002 (DC/DC converter) in accordance with the output (logical level) of the duty control circuit 2005 (S5). A switching action causes the DC/DC converter 2002 to receive an electric energy from the dc voltage V.sub.BB so as to supply a predetermined dc current to the secondary side of the high-frequency transformer T (S6). By repeating steps S1-S6, it is possible to supply a desired current or voltage to the load 2001.
The switching power supply as described above is generally constructed to provide a necessary power supply at a fixed level (for example, +5V or +3.5V) derived from a predetermined main power supply (for example, AC100V or DC48V). The object of such a power supply unit is to provide a stable output efficiently. The requirement for a variable output only arises from a need to fine-tuning the power supply.
For example, the function for supplying a power to a terminal in a subscriber circuit requires is known as power feed. A power feed circuit is a type of power supply characterized by a small power output of approximately 2W. The power feed circuit is required to exercise complex control for switching from a constant current to a constant voltage depending on a line resistance. Such a requirement is absent in the conventional switching power supply. The technology for a switching power supply begins to be required in the subscriber circuit for the purpose of saving power.